HD6417705F133V Datasheet, PDF (498/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit Bit Name
4
EP2CLR
3, 2 
1
EP0oCLR
0
EP0iCLR
Initial Value R/W
Undefined W
Undefined 
Undefined W
Undefined W
Description
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
Reserved
The write value should always be 0.
EP0o Clear
Writing 1 to this bit initializes the endpoint 0 receive
FIFO buffer.
EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.
18.3.18 DMA Transfer Setting Register (DMAR)
DMA transfer can be carried out between the endpoint 1 and 2 data registers and memory by
means of the on-chip direct memory access controller (DMA). Dual address transfer is performed
in bytes. To start DMA transfer, DMAC settings must be made in addition to the settings in this
register.
Bit Bit Name
7 to 2 
Initial Value R/W Description
0
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 450 of 690