HD6417705F133V Datasheet, PDF (629/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.5 Boundary Scan
A command can be set in SDIR by the UDI to place the UDI pins in boundary scan mode
stipulated by JTAG.
23.5.1 Supported Instructions
This LSI supports the three essential instructions defined in the JTAG standard (BYPASS,
SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and
HIGHZ).
1. BYPASS:
The BYPASS instruction is an essential standard instruction that operates the bypass register.
This instruction shortens the shift path to speed up serial data transfer involving other chips on
the printed circuit board. While this instruction is executing, the test circuit has no effect on the
system circuits. The upper four bits of the instruction code are 1111.
2. SAMPLE/PRELOAD:
The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the
boundary scan register, outputs values from the scan path, and loads data onto the scan path.
When this instruction is executing, this LSI's input pin signals are transmitted directly to the
internal circuitry, and internal circuit values are directly output externally from the output pins.
This LSI's system circuits are not affected by execution of this instruction. The upper four bits
of the instruction code are 0100.
In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the
internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is
latched into the boundary scan register and read from the scan path. Snapshot latching is
performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching
does not affect normal operation of this LSI.
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary
scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD
operation, when the EXTEST instruction was executed an undefined value would be output
from the output pin until completion of the initial scan sequence (transfer to the output latch)
(with the EXTEST instruction, the parallel output latch value is constantly output to the output
pin).
Rev. 2.00, 09/03, page 581 of 690