HD6417705F133V Datasheet, PDF (335/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Note: WTCNT differs from other registers in that it is more difficult to write to. See section
10.2.3, Notes on Register Access, for details.
10.2.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the count, overflow flags, and enable bits.
WTCSR holds its value in an internal reset due to the WDT overflow. WTCSR is initialized to
H'00 only by a power-on reset using the RESETP pin.
When used to count the clock settling time for canceling a software standby, it retains its value
after counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper
byte. Use a byte access to read WTCSR.
Note: WTCSR differs from other registers in that it is more difficult to write to. See section
10.2.3, Notes on Register Access, for details.
Rev. 2.00, 09/03, page 287 of 690