HD6417705F133V Datasheet, PDF (240/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.6.2 Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 7.8.
T₁
Tw
T₂
CKIO
A25 to A0
CSn
RD/WR
Read
RD
Data
Write
WEn
Data
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)
Rev. 2.00, 09/03, page 192 of 690