HD6417705F133V Datasheet, PDF (219/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
10
W3
9
W2
8
W1
7
W0
6
WM
5 to 2 
1
HW1
0
HW0
Initial
Value R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
Description
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the first
read/write access cycle.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
External Wait Mask Specification
Specifies whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Delay Cycles from RD, WEn negation to Address, CSn
negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00, 09/03, page 171 of 690