HD6417705F133V Datasheet, PDF (289/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

8.2 Input/Output Pins
The external pins for the DMAC are described below.
Table 8.1 lists the configuration of the pins that are connected to external bus. The DMAC has
pins for 2 channels (channels 0 and 1) for external bus use. Channel 0 has the DMA transfer end
signal.
Table 8.1 Pin Configuration
Channel Name
Symbol I/O
0
DMA transfer request DREQ0 I
DMA transfer request DACK0 O
acknowledge
DMA transfer end
TEND0 O
1
DMA transfer request DREQ1 I
DMA transfer request DACK1 O
acknowledge
Function
DMA transfer request input from
external device to channel 0
DMA transfer request acknowledge
output from channel 0 to external device
Transfer end output in channel 0
DMA transfer request input from
external device to channel 1
DMA transfer request acknowledge
output from channel 1 to external device
8.3 Register Descriptions
The DMAC has the following registers. See section 24, List of Registers, for the addresses of
these registers and the states of them in each processing state. The SAR for channel 0 is expressed
such as SAR_0.
1. Channel 0
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
2. Channel 1
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register _1 (CHCR_1)
Rev. 2.00, 09/03, page 241 of 690