HD6417705F133V Datasheet, PDF (301/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 8.2 is a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?^*1
Yes
Transfer (1 transfer unit);
DMATCR − 1 → DMATCR, SAR and DAR
updated
*²
Bus mode,
*³
transfer request mode,
DREQ detection method
No
DMATCR = 0?
Yes
TE = 1
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer aborted
DEI interrupt request (when IE = 1)
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer end
Normal end
Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE bits are 0 and the DE and DME
bits are set to 1.
2. DREQ = level detection in burst mode (external request), or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 8.2 DMAC Transfer Flowchart
Rev. 2.00, 09/03, page 253 of 690