HD6417705F133V Datasheet, PDF (170/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated. The vector address of the TLB miss exception is VBR + H'0400. To speed up
TLB miss processing, the offset differs from other exceptions.
TLB Invalid Exception:
• Conditions
Comparison of TLB addresses shows address match but V = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated.
TLB Protection Exception:
• Conditions
When a hit access violates the TLB protection information (PR bits)
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
Rev. 2.00, 09/03, page 122 of 690