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HD6417705F133V Datasheet, PDF (633/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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Section 24 List of Registers
This section gives information on the on-chip I/O registers and is configured as described
below.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
⢠Descriptions by functional module, in order of the corresponding section numbers
Entries that consist of  lines are for separation of the functional modules.
⢠Access to reserved addresses which are not described in this list is prohibited.
⢠When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the
presumption of a big-endian system.
2. Register Bits
⢠Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
⢠Reserved bits are indicated by  in the bit name.
⢠No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
⢠When registers consist of 16 or 32 bits, bits are described from the MSB side.
The order in which bytes are described is on the presumption of a big-endian system.
3. Register States in Each Operating Mode
⢠Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
⢠For the initial state of each bit, refer to the description of the register in the corresponding
section.
⢠The register states described are for the basic operating modes. If there is a specific reset for
an on-chip module, refer to the section on that on-chip module.
Rev. 2.00, 09/03, page 585 of 690
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