HD6417705F133V Datasheet, PDF (607/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

occurs at a delayed branch instruction or its delay slot, the break may not actually take place
until the first instruction at the branch destination.
22.3.4 Sequential Break
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0.
2. In sequential break specification, the L or I bus can be selected and the execution times break
condition can be also specified. For example, when the execution times break condition is
specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
22.3.5 Value of Saved Program Counter
When a break occurs, the address of the instruction from where execution is to be resumed is
saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break
condition, the instruction at which the break should occur can be clearly determined (except for
when data is included in the break condition). If the I bus is specified as a break condition, the
instruction at which the break should occur cannot be clearly determined.
Rev. 2.00, 09/03, page 559 of 690