HD6417705F133V Datasheet, PDF (185/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.4.3 IRL Interrupts
IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher of those
indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level
interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request
(interrupt priority level 0). Figure 6.2 shows an examples of an IRL interrupt connection. Table
6.3 shows IRL pin and interrupt levels.
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every peripheral clock remain unchanged for two consecutive cycles, so that no
transient level on the IRL pin change is detected. In standby mode, as the peripheral clock is
stopped, noise cancellation is performed using the clock for the RTC instead. Therefore when the
RTC is not used, recovery from standby mode by means of IRL interrupts cannot be performed in
standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt
processing.
Interrupt
request
Priority
encoder
4
IRL3 to IRL0
This LSI
IRL3 to IRL0
Figure 6.2 Example of IRL Interrupt Connection
Rev. 2.00, 09/03, page 137 of 690