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HD6417705F133V Datasheet, PDF (583/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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A/D conversion time (tCONV)
A/D conversion start delay time (tD) Analog input sampling time (tSPL)
Write cycle A/D
synchronization time
PÏ
Address
Internal
write signal
Analog input
sampling signal
Write timing of ADST
A/D converter
Idle time
Sample and hold A/D conversion executed
ADF
A/D conversion ended
Figure 21.2 A/D Conversion Timing
Table 21.3 A/D Conversion Time (Single Mode)
CKS1 = 1,
CKS0 = 0
Symbol Min Typ Max
A/D conversion start tD
delay
18 â 21
Input sampling time tSPL
â 129 â
A/D conversion time tCONV
535 â 545
Note: Values in the table are numbers of states for PÏ.
CKS1 = 0,
CKS0 = 1
Min Typ Max
10 â 13
â 65 â
275 â 285
CKS1 = 0,
CKS0 = 0
Min Typ Max
6
â9
â 33 â
141 â 151
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1
0
0
1
1
CKS0
0
1
0
1
Conversion Time (cycles)
128 (fixed)
256 (fixed)
512 (fixed)
Unused
Rev. 2.00, 09/03, page 535 of 690
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