HD6417705F133V Datasheet, PDF (149/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4.3 Operation
4.3.1 Searching the Cache
If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1,
P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the
cache. Figure 4.2 illustrates the method by which the cache is searched. The cache is a physical
cache and holds physical addresses in its address section. The following will be described for the
32-kbyte mode as an example.
Entries are selected using bits 12 to 4 of the address (virtual) of the access to memory and the tag
address of that entry is read. The virtual address (bits 31 to 10) of the access to memory and the
physical address (tag address) read from the address array are compared. The address comparison
uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a
cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V
= 0), a cache miss occurs. Figure 4.2 shows a hit on way 1.
Virtual address
31
13 12
4 3 210
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
MMU
0 V U Tag address
1
LW0 LW1 LW2 LW3
511
Physical address
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 4.2 Cache Search Scheme
Rev. 2.00, 09/03, page 101 of 690