HD6417705F133V Datasheet, PDF (599/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
9, 8 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
DBEB 0
R/W Data Break Enable B
Selects whether or not the data bus condition is included in
the break condition of channel B.
0: No data bus condition is included in the condition of channel
B
1: The data bus condition is included in the condition of
channel B
6
PCBB 0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
0: PC break of channel B is set before instruction execution
1: PC break of channel B is set after instruction execution
5, 4 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
SEQ 0
R/W Sequence Condition Select
Selects two conditions of channels A and B as independent or
sequential conditions.
0: Channels A and B are compared under independent
conditions
1: Channels A and B are compared under sequential
conditions (channel A, then channel B)
2, 1 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
ETBE 0
R/W Number of Execution Times Break Enable
Enables the execution-times break condition only on channel
B. If this bit is 1 (break enable), a user break is issued when
the number of satisfied break conditions matches with the
number of execution times that is specified by BETR.
0: The execution-times break condition is disabled on channel
B
1: The execution-times break condition is enabled on channel
B
Rev. 2.00, 09/03, page 551 of 690