HD6417705F133V Datasheet, PDF (432/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name Value R/W Description
3
STOP 0
R/W Stop Bit Length
Selects one or two bits as the stop bit length. In
reception, only the first stop bit is checked, regardless
of the STOP bit setting. If the second stop bit is 1, it is
treated as a stop bit; if it is 0, it is treated as the start bit
of the next transmit character.
This setting is only valid in asynchronous mode. In
clock synchronous mode, this setting is invalid since
stop bits are not added.
0: One stop bit^*1
1: Two stop bits^*2
Notes: 1. In transmission, a single 1-bit (stop bit) is
added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are
added to the end of a transmit character
before it is sent.
2

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
CKS1 0
R/W Clock Select
0
CKS0 0
R/W _{Select the clock source for the on-chip baud rate}
generator.
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: When the clock synchronous mode is selected (C/A bit = 1), the bits other than CKS1 and
CKS0 bits are all fixed to 0.
Rev. 2.00, 09/03, page 384 of 690