HD6417705F133V Datasheet, PDF (603/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.14 Break ASID Register B (BASRB)
BASRB is an 8-bit readable/writable register that specifies ASID which becomes the break
condition for channel B. BASRB is in CCN.
Bit
7 to 0
Bit
Name
BASB7
to
BASB0
Initial
Value R/W

R/W
Description
Break ASID B
Store ASID (bits 7 to 0) which is the break condition for
channel B.
22.3 Operation
22.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and corresponding ASID are set in the break address registers (BARA and
BARB) and break ASID registers (BASRA and BASRB in CNN). The masked addresses are
set in the break address mask registers (BAMRA and BAMRB). The break data is set in the
break data register (BDRB). The masked data is set in the break data mask register (BDMRB).
The bus break conditions are set in the break bus cycle registers (BBRA and BBRB). Three
groups of BBRA and BBRB (L bus cycle/I bus cycle select, instruction fetch/data access
select, and read/write select) are each set. No user break will be generated if even one of these
groups is set with 00. The respective conditions are set in the bits of the break control register
(BRCR). Make sure to set all registers related to breaks before setting BBRA/BBRB.
2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and
sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match
flag (SCMFDA or SCMFDB) for the appropriate channel.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
4. There is a chance that the data access break and its following instruction fetch break occur
around the same time. There will be only one break request to the CPU, but these two break
channel match flags could be both set.
Rev. 2.00, 09/03, page 555 of 690