HD6417705F133V Datasheet, PDF (442/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W
Description
2 PER 0
R
Parity Error
Indicates a parity error in the data read from SCFRDR in
asynchronous mode.
0: There is no parity error in the receive data read from
SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When there is no parity error in SCFRDR read data
1: There is a parity error in the receive data read from
SCFRDR
[Setting condition]
When there is a parity error in SCFRDR read data
1 RDF 0
R/(W)^* Receive FIFO Data Full
Indicates that the received data has been transferred from
SCRSR to SCFRDR, and the number of receive data bytes
in SCFRDR is equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in the FIFO control
register (SCFCR).
0: The number of receive data bytes in SCFRDR is less
than the receive trigger set number
[Clearing conditions]
• Power-on reset or manual reset
• When SCFRDR is read until the number of receive data
bytes in SCFRDR falls below the receive trigger set
number, and 0 is written to RDF after reading RDF = 1
1: The number of receive data bytes in SCFRDR is equal to
or greater than the receive trigger set number
[Setting condition]
When SCFRDR contains at least the receive trigger set
number of receive data bytes^*1
Note: 1. SCFRDR is a 64-byte FIFO register. When RDF =
1, at least the receive trigger set number of data
bytes can be read. If data is read when SCFRDR
is empty, an undefined value will be returned. The
number of receive data bytes in SCFRDR is
indicated by the lower bits of SCFDR.
Rev. 2.00, 09/03, page 394 of 690