HD6417705F133V Datasheet, PDF (213/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CS4WCR, CS5AWCR
Bit
Bit Name
31 to 19 
Initial
Value R/W
0
R
18
WW2 0
R/W
17
WW1 0
R/W
16
WW0 0
R/W
15 to 13 
0
R
12
SW1 0
R/W
11
SW0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read access
wait)
001: 0 cycle
010: 1 cycles
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to RD,
WEn Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00, 09/03, page 165 of 690