HD6417705F133V Datasheet, PDF (87/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

The little endian mode can also be specified as data format. Either big-endian or little-endian mode
can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor
operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian
mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of the general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip device registers assigned to memory are accessed
in big endian mode. Note that the available access size (byte, word, or long word) differs in each
register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
31
23
15
7
0
Byte position
in R0
[7:0]
[15:8] [7:0]
[31:24] [23:16] [15:8] [7:0]
Byte position
in memory
[7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(a) Byte access
Example: MOV.B R0, @R1
(R1 = Address 4n)
[15:8] [7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(b) Word access
Example: MOV.W R0, @R1
(R1 = Address 4n)
[31:24] [23:16] [15:8] [7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(c) Longword access
Example: MOV.L R0, @R1
(R1 = Address 4n)
Figure 2.8 Data Format on Memory (Little Endian Mode)
Rev. 2.00, 09/03, page 39 of 690