HD6417705F133V Datasheet, PDF (713/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
Trc
Trc
t_AD3
t_AD3
t_AD3
t_AD3
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_CASD2
(Hi-Z)
t_RWD2
BS
CKE
(High)
DACKn^*2
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.40 Synchronous DRAM Auto-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode)
Rev. 2.00, 09/03, page 665 of 690