HD6417705F133V Datasheet, PDF(425/741 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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HD6417705F133V Datasheet, PDF (425/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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Figure 16.1 shows a block diagram of the SCIF.

Module data bus

Peripheral

bus

RxD

SCK

TxD

CTS

RTS

SCFRDR

(64-stage)

SCRSR

SCFTDR

(64-stage)

SCTSR

Parity check

Parity

generation

SCFDR

SCFCR

SCFER

SCSSR

SCSCR

SCSMR

SCTDSR

SCBRR

Baud rate

generator

Transmission/

reception control

Clock

External clock

Note:

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

SCFER:

SCSSR:

SCBRR:

SCFCR:

SCFDR:

SCTDSR:

SSCCIFI4F

FIFO error count register

Serial status register

Bit rate register

FIFO control register

FIFO data count register

Transit data stop register

Figure 16.1 Block Diagram of SCIF

PÏ

PÏ/4

PÏ/16

PÏ/64

SCIF

interrupt

Rev. 2.00, 09/03, page 377 of 690

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