HD6417705F133V Datasheet, PDF (292/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Descriptions
17
AM
0
R/W Acknowledge Mode
Selects whether DACK is output in data read cycle or in data
write cycle in dual address mode.
In single address mode, DACK is always output regardless of
the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1. This bit is
always read as 0 in CHCR_2 and CHCR_3. The write value
should always be 0.
0: DACK output in read cycle (Dual address mode)
1: DACK output in write cycle (Dual address mode)
16
AL
0
R/W Acknowledge Level
Specifies the DACK signal output is high active or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit is
always read as 0 in CHCR_2 and CHCR_3. The write value
should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
15
DM1 0
R/W Destination Address Mode
14
DM0 0
R/W Specify whether the DMA destination address is incremented,
decremented, or left fixed. (In single address mode, the DM1
and DM0 bits are ignored when data is transferred to an
external device with DACK.)
00: Fixed destination address
(setting prohibited in 16-byte transfer)
01: Destination address is incremented (+1 in byte-size
transfer, +2 in word-size transfer, +4 in longword-size
transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in byte-size
transfer, –2 in word-size transfer, –4 in longword-size
transfer, setting prohibited in 16-byte transfer)
11: Setting prohibited
Rev. 2.00, 09/03, page 244 of 690