|
HD6417705F133V Datasheet, PDF (109/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
|
◁ |
Instruction
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
STC.L SSR,@âRn
0100nnnn00110011 Rnâ4âRn, SSRâ(Rn)
â
1
â
STC.L SPC,@âRn
0100nnnn01000011 Rnâ4âRn, SPCâ(Rn)
â
1
â
STC.L R0_BANK,@âRn 0100nnnn10000011 Rnâ4âRn, R0_BANKâ(Rn)
â
1
â
STC.L R1_BANK,@âRn 0100nnnn10010011 Rnâ4âRn, R1_BANKâ(Rn)
â
1
â
STC.L R2_BANK,@âRn 0100nnnn10100011 Rnâ4âRn, R2_BANKâ(Rn)
â
1
â
STC.L R3_BANK,@âRn 0100nnnn10110011 Rnâ4âRn, R3_BANKâ(Rn)
â
1
â
STC.L R4_BANK,@âRn 0100nnnn11000011 Rnâ4âRn, R4_BANKâ(Rn)
â
1
â
STC.L R5_BANK,@âRn 0100nnnn11010011 Rnâ4âRn, R5_BANKâ(Rn)
â
1
â
STC.L R6_BANK,@âRn 0100nnnn11100011 Rnâ4âRn, R6_BANKâ(Rn)
â
1
â
STC.L R7_BANK,@âRn 0100nnnn11110011 Rnâ4âRn, R7_BANKâ(Rn)
â
1
â
STS MACH,Rn
0000nnnn00001010 MACHâRn
â
1
â
STS MACL,Rn
0000nnnn00011010 MACLâRn
â
1
â
STS PR,Rn
0000nnnn00101010 PRâRn
â
1
â
STS.L MACH,@âRn 0100nnnn00000010 Rnâ4âRn, MACHâ(Rn)
â
1
â
STS.L MACL,@âRn 0100nnnn00010010 Rnâ4âRn, MACLâ(Rn)
â
1
â
STS.L PR,@âRn
0100nnnn00100010 Rnâ4âRn, PRâ(Rn)
â
1
â
TRAPA #imm
11000011iiiiiiii
Unconditional trap exception â
occurs*2
8
â
Notes: The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased in the following conditions.
a.
If there is a conflict between an instruction fetch and a data access
b.
If the destination register of a load instruction (memory â register) is also
used by the following instruction.
For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the
operand size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp ; PC relative
1. Number of states before the chip enters the sleep state.
2. For details, refer to section 5, Exception Handling.
Rev. 2.00, 09/03, page 61 of 690
|
▷ |