HD6417705F133V Datasheet, PDF (186/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 6.3 IRL3 to IRL0 Pins and Interrupt Levels
IRL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IRL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
6.4.4 PINT Interrupt
PINT interrupts are input from pins PINT0 to PINT15 with a level. The priority level can be set by
the interrupt priority level setting register D (IPRD) in a range from levels 0 to 15, in the unit of
PINT0 to PINT7 or PINT8 to PINT15. The PINT interrupt level should be held until the interrupt
is accepted and interrupt handling is started.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by PINT interrupt
processing. PINT interrupts can wake the chip up from the standby state when the relevant
interrupt level is higher than I3 to I0 in SR (but only when the RTC is used, the clock for the RTC
is used to wake the chip up from the standby state).
6.4.5 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following 10 modules:
• Direct memory access controller (DMAC)
• Serial communication interfaces (SCIF0 and SCIF2)
• A/D converter (ADC)
Rev. 2.00, 09/03, page 138 of 690