HD6417705F133V Datasheet, PDF (251/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex
Output (2)-1
Setting
A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0]
11 (32 bits) 01 (12 bits)
01 (9 bits)
Output Pin of Row Address Column Address Synchronous DRAM
This LSI
Output Cycle Output Cycle
Pin
Function
A17
A26
A17
Unused
A16
A25
A16
A15
A24^*2
A24^*2
A14
A23^*2
A23^*2
A13 (BA1)
A12 (BA0)
Specifies bank
A13
A22
A12
A21
A13
L/H^*1
A11
A10/AP
Address
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
Unused
A0
A9
A0
Example of connected memory
256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1 device
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2 devices
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 2.00, 09/03, page 203 of 690