HD6417705F133V Datasheet, PDF (371/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Compare Match Timer (CMT)
The DMAC has an on-chip compare match timer (CMT) to generate a DMA transfer request. The
CMT has 16-bit counter.
Figure 13.1 shows a CMT block diagram.
13.1 Features
• Four types of counter input clock can be selected.
One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected.
• Generates a DMA transfer request when compare match occurs. (The CPU interrupt is not
supported.)
• When the CMT is not used, the operation can be halted by stopping the clock supply to the
CMT so that the power consumption can be reduced.
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Control circuit
Clock selection
Module bus
Bus
interface
CMT
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match constant register
CMCNT: Compare match counter
Internal bus
Figure 13.1 CMT Block Diagram
TIMCMT2A_000020020100
Rev. 2.00, 09/03, page 323 of 690