HD6417705F133V Datasheet, PDF (609/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.3.6 PC Trace
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
 If a branch occurs due to a branch instruction, the address of the branch instruction is saved
in BRSR and the address of the branch destination instruction is saved in BRDR.
 If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception
occurrence is saved in BRSR and the start address of the exception handling routine is
saved in BRDR.
3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
Rev. 2.00, 09/03, page 561 of 690