HD6417705F133V Datasheet, PDF (506/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

3. Data Stage (Control-Out)
USB function
OUT token reception
Application
1 written
to TRG.EP0s
RDFN?
Yes
No
NACK
Data reception from host
ACK
Set EP0o reception
complete flag
(IFR0.EP0o TS = 1)
Interrupt request
Clear EP0o reception
complete flag
(IFR0.EP0o TS = 0)
OUT token reception
Read data from EP0o
receive data size register
(EPSZ0o)
1 written
to TRG.EP0o
RDFN?
Yes
No
NACK
Read data from EP0o
data register (EPDR0o)
Write 1 to EP0o read
complete bit
(TRG.EP0o RDFN = 1)
Figure 18.7 Data Stage (Control-Out) Operation
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (EP0oTS bit in
IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit,
empties the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 2.00, 09/03, page 458 of 690