HD6417705F133V Datasheet, PDF (24/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.2 Pin Configuration ........................................................................................................ 151
7.3 Area Overview............................................................................................................. 152
7.3.1 Address Map................................................................................................... 152
7.3.2 Memory Bus Width ......................................................................................... 154
7.3.3 Shadow Space ................................................................................................. 155
7.4 Register Descriptions................................................................................................... 155
7.4.1 Common Control Register (CMNCR).............................................................. 156
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B).... 158
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) . 161
7.4.4 SDRAM Control Register (SDCR) .................................................................. 174
7.4.5 Refresh Timer Control/Status Register (RTCSR) ............................................. 177
7.4.6 Refresh Timer Counter (RTCNT) .................................................................... 179
7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 179
7.4.8 Reset Wait Counter (RWTCNT)...................................................................... 180
7.5 Endian/Access Size and Data Alignment ...................................................................... 180
7.6 Normal Space Interface................................................................................................ 187
7.6.1 Basic Timing................................................................................................... 187
7.6.2 Access Wait Control........................................................................................ 192
7.6.3 CSn Assert Period Expansion .......................................................................... 194
7.7 Address/Data Multiplex I/O Interface........................................................................... 195
7.8 SDRAM Interface........................................................................................................ 198
7.8.1 SDRAM Direct Connection ............................................................................. 198
7.8.2 Address Multiplexing ...................................................................................... 200
7.8.3 Burst Read ...................................................................................................... 212
7.8.4 Single Read..................................................................................................... 214
7.8.5 Burst Write ..................................................................................................... 215
7.8.6 Single Write .................................................................................................... 217
7.8.7 Bank Active .................................................................................................... 218
7.8.8 Refreshing....................................................................................................... 225
7.8.9 Low-Frequency Mode ..................................................................................... 228
7.8.10 Power-On Sequence ........................................................................................ 229
7.9 Burst ROM Interface.................................................................................................... 231
7.10 Byte-Selection SRAM Interface ................................................................................... 233
7.11 Wait between Access Cycles ........................................................................................ 235
7.12 Bus Arbitration ............................................................................................................ 235
7.13 Others.......................................................................................................................... 237
Section 8 Direct Memory Access Controller (DMAC)....................................239
8.1 Features....................................................................................................................... 239
8.2 Input/Output Pins......................................................................................................... 241
8.3 Register Descriptions................................................................................................... 241
8.3.1 DMA Source Address Registers (SAR)............................................................ 242
8.3.2 DMA Destination Address Registers (DAR) .................................................... 242
Rev. 2.00, 09/03, page xxii of xlvi