HD6417705F133V Datasheet, PDF (395/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Example of Buffer Operation Setting Procedure: Figure 14.9 shows an example of the buffer
operation setting procedure.
Buffer operation
Set buffer operation
[1]
Set rewriting timing
[2]
Set external pin function [3]
[1] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[2] Set rewriting timing from the buffer register with
bit BFWT in TMDR.
[3] Set the external pin function in pin function
controller (PFC).
[4] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[4]
<Buffer operation>
Figure 14.9 Example of Buffer Operation Setting Procedure
Example of Buffer Operation
Figure 14.10 shows an operation example in which PWM mode has been designated for channel 0,
and buffer operation has been designated for TGRA and TGRC. The settings used in this example
are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at counter
clearing. Rewriting timing from the buffer register is set at counter clearing.
As buffer operation has been set, when compare match A occurs the output changes. When
counter clearing occurs by TGRB, the output changes and the value in buffer register TGRC is
simultaneously transferred to timer general register TGRA. This operation is repeated each time
compare match A occurs.
For details of PWM modes, see section 14.4.4, PWM Modes.
Rev. 2.00, 09/03, page 347 of 690