HD6417705F133V Datasheet, PDF (263/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.5 Burst Write
A burst write occurs in the following cases in this LSI.
• Copyback of the cache
• 16-byte transfer in DMAC (access to non-cacheable region)
• Access size in writing is larger than data bus width.
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is
connected to a 32-bit data bus.
The relationship between the access size and the number of bursts is shown in table 7.16.
Rev. 2.00, 09/03, page 215 of 690