HD6417705F133V Datasheet, PDF (613/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Break Condition Specified for an L Bus Data Access Cycle
Register specifications:
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
• Channel A
Address:
H'00123456, Address mask: H'00000000, ASID = H'80
Bus cycle: L bus/data access/read (operand size is not included in the condition)
• Channel B
Address:
H'000ABCDE, Address mask: H'000000FF, ASID = H'70
Data:
H'0000A512, Data mask: H'00000000
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from ASID = H'80 and address
H'00123454, word read from address H'00123456, or byte read from address H'00123456.
On channel B, a user break occurs when word H'A512 is written in ASID = H'70 and
addresses H'000ABC00 to H'000ABCFE.
Break Condition Specified for an I Bus Data Access Cycle
Register specifications:
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
• Channel A
Address:
H'00314156, Address mask: H'00000000, ASID = H'80
Bus cycle:
I bus/instruction fetch/read (operand size is not included in the
condition)
• Channel B
Address:
H'00055555, Address mask: H'00000000, ASID = H'70
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: I bus/data access/write/byte
On channel A, a user break occurs when instruction fetch is performed for ASID = H'80
and address H'00314156 in the memory space.
On channel B, a user break occurs when byte data H'7* is written in address H'00055555
with ASID = H'70 on the I bus.
Rev. 2.00, 09/03, page 565 of 690