HD6417705F133V Datasheet, PDF (293/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Descriptions
13
SM1 0
R/W Source Address Mode
12
SM0 0
R/W Specifies whether the DMA source address is incremented,
decremented, or left fixed. (In single address mode, the SM1
and SM0 bits are ignored when data is transferred from an
external device with DACK.)
00: Fixed source address
(setting prohibited in 16-byte transfer)
01: Source address is incremented (+1 in byte-size transfer, +2
in word-size transfer, +4 in longword-size transfer, +16 in
16-byte transfer)
10: Source address is decremented (–1 in byte-size transfer, –2
in word-size transfer, –4 in longword-size transfer, setting
prohibited in 16-byte transfer)
11: Setting prohibited
11
RS3
0
10
RS2
0
9
RS1
0
8
RS0
0
R/W Resource Select
R/W Specifies which transfer requests will be sent to the DMAC. The
R/W ^{changing of transfer request source should be done in the state}
that the DMA enable bit (DE) is set to 0.
R/W _{0000: External request, dual address mode}
0001: Setting prohibited
0010: External request/single address mode
External address space → external device with DACK
0011: External request/single address mode
External device with DACK → external address space
0100: Auto request
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1000: DMA extended resource selector specification
1001: Setting prohibited
1010: Setting prohibited
1011: Setting prohibited
1100: Setting prohibited
1101: Setting prohibited
1110: Peripheral module request, A/D converter
1111: Peripheral module request, CMT
Note: External request specification is valid only in CHCR_0
and CHCR_1. None of the external request specification
can be set in channels CHCR_2 and CHCR_3.
Rev. 2.00, 09/03, page 245 of 690