HD6417705F133V Datasheet, PDF (273/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.8 Refreshing
This LSI has a function for controlling synchronous DRAM refreshing. Auto-refreshing can be
performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous
refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If synchronous DRAM is not
accessed for a long period, self-refresh mode, in which the power consumption for data retention
is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
1. Auto-refreshing
Refreshing is performed for the number of times specified by bits RRC[2:0] in RTCSR at
intervals determined by the input clock selected by bits CKS[2:0] in RTCSR, and the value set
in RTCOR. The value of these bits should be set so as to satisfy the refresh interval stipulation
for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the
RMODE and RFSH bits in SDCR, then make bits CKS[2:0] and RRC[2:0] settings in RTCSR.
When the clock is selected by bits CKS[2:0], RTCNT starts counting up from the value at that
time. The RTCNT value is constantly compared with the RTCOR value, and if the two values
are the same, a refresh request is generated and auto-refresh is performed for the number of
times specified by bits RRC[2:0]. At the same time, RTCNT is cleared to zero and the count-
up is restarted. Figure 7.26 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the
banks to pre-charged state from active state when some bank is being pre-charged. Then REF
command is issued in the Trr cycle after inserting idle cycles of which number is specified by
the TRP[1:0] bits in CSnWCR. A new command is not issued for the duration of the number
of cycles specified by the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits
must be set so as to satisfy the SDRAM refreshing cycle time stipulation (t_RC). A NOP cycle is
inserted between the Tp cycle and Trr cycle when the setting value of the TRP[1:0] bits in
CSnWCR is longer than or equal to 2 cycles.
Rev. 2.00, 09/03, page 225 of 690