HD6417705F133V Datasheet, PDF (491/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.3 Interrupt Select Register 0 (ISR0)
ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0
(IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the
interrupt corresponding to the bit will be USI0 (USB interrupt 0). If the USB issues an interrupt
request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USI1 (USB
interrupt 1). If interrupts occur simultaneously, USI0 has priority by default.
Bit Bit Name
7
BRST
6
EP1FULL
5
EP2TR
4
EP2EMPTY
3
SETUPTS
2
EP0oTS
1
EP0iTR
0
EP0iTS
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Bus Reset
EP1 FIFO Full
EP2 Transfer Request
EP2 FIFO Empty
Setup Command Receive Complete
EP0o Receive Complete
EP0i Transfer Request
EP0i Transmit Complete
18.3.4 Interrupt Select Register 1 (ISR1)
ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1
(IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR1 is cleared to 0, the
interrupt corresponding to the bit will be USI0 (USB interrupt 0). If the USB issues an interrupt
request to the INTC when a bit in ISR1 is set to 1, the corresponding interrupt will be USI1 (USB
interrupt 1). If interrupts occur simultaneously, USI0 has priority by default.
Bit Bit Name Initial Value R/W
7 to 3 
0
R
2
EP3TR
1
R/W
1
EP3TS
1
R/W
0
VBUS
1
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
EP3 Transfer Request
EP3 Transmit Complete
USB Bus Connect
Rev. 2.00, 09/03, page 443 of 690