HD6417705F133V Datasheet, PDF (17/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Item
22.2.10 Execution Times
Break Register (BETR)
Page
552
Revisions (See Manual for Details)
Note added
Note: If the channel B brake condition set to during instruction fetch cycles and any of the
instructions below perform breaks, BETR is not decremented when the first break occurs.
The decremented values are listed below.
Instruction
Value
Decremented
Instruction
Value
Decremented
RTE
4
DMULS.L Rm,Rn
2
DMULU.L Rm,Rn
2
MAC.L @Rm+,@Rn+
2
MAC.W @Rm+,@Rn+
2
MUL.L Rm,Rn
3
AND.B #imm,@(R0,GBR)
3
OR.B #imm,@(R0,GBR)
3
TAS.B @Rn
3
TST.B #imm,@(R0,GBR)
3
XOR.B #imm,@(R0,GBR) 3
LDC Rm,SR
4
LDC Rm,GBR
4
LDC Rm,VBR
4
LDC Rm,SSR
4
LDC Rm,SPC
4
LDC Rm,R0_BANK
4
LDC Rm,R1_BANK
4
LDC Rm,R2_BANK
4
LDC Rm,R3_BANK
4
LDC Rm,R4_BANK
4
LDC Rm,R5_BANK
4
LDC Rm,R6_BANK
4
LDC Rm,R7_BANK
4
LDC.L @Rm+,SR
6
LDC.L @Rm+,GBR
4
LDC.L @Rm+,VBR
4
LDC.L @Rm+,SSR
4
LDC.L @Rm+,SPC
4
LDC.L @Rm+,R0_BANK
4
LDC.L @Rm+,R1_BANK
4
LDC.L @Rm+,R2_BANK
4
LDC.L @Rm+,R3_BANK
4
LDC.L @Rm+,R4_BANK
4
LDC.L @Rm+,R5_BANK
4
LDC.L @Rm+,R6_BANK
4
LDC.L @Rm+,R7_BANK
4
LDC.L @Rn+,MOD
4
LDC.L @Rn+,RS
4
LDC.L @Rn+,RE
4
LDC Rn,MOD
4
LDC Rn,RS
4
LDC Rn,RE
4
BSR label
2
BSRF Rm
2
JSR @Rm
2
23.2 Input/Output Pins
569
23.3.3 Boundary Scan
570
Register (SDBSR)
23.5.2 Points for Attention 582
24.1 Register Addresses 592
(by functional module, in
order of the corresponding
section numbers)
Note * added
Note: * The pull-up MOS turns on if the pin function
controller (PFC) is used to select other functions (UDI).
Description amended
SDBSR is a 385-bit shift register, located on the PAD, for
controlling the input/output pins of this LSI.
Item 7 added under “23.5.2 Points for Attention”
7. The CKIO cock should operate during boundary scan.
The MD[2:0] pin should be set to the clock mode used
during normal operation, and EXTAL and CKIO should be
set within the frequency range specified in the Clock Pulse
Generator (CPG) section.
As during normal operation, the boundary scan test should
be performed after allowing sufficient settling time for the
crystal oscillator, PLL1, and PLL2.
Access size of EP1 data register and EP2 data register
amended to 8/32
Rev. 2.00, 09/03, page xv of xlvi