HD6417705F133V Datasheet, PDF (569/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

20.11.2 Port L Data Register (PLDR)
PLDR is an 8-bit read-only register that stores data for pins PTL3 to PTL0. Bits PL3DT to PL0DT
correspond to pins PTL3 to PTL0. If the port is read, the corresponding pin level is read.
Bit
Initial
Bit Name Value R/W
7 to 4 —
0
R
3 to 0 PL3DT 0
R
to
PL0DT
Description
Reserved
These bits are always read as 0.
Table 20.11 shows the function of PLDR.
Table 20.11 Port L Data Register (PLDR) Read/Write Operation
PLCR State
PLnMD1 PLnMD0 Pin State
Read
0
0
Other function Read as 0
Write
Invalid (no effect on pin state)
1
1
0
1
Note: n = 0 to 3
Setting
prohibited
Setting
prohibited
Input (Pull-up
MOS off)
—
—
Pin state
—
—
Invalid (no effect on pin state)
20.12 Port M
Port M is a 6-bit input/output port with the pin configuration shown in figure 20.12. Each pin has
an input pull-up MOS, which is controlled by the port M control register (PMCR) in the PFC.
Port M
PTM6 (input/output)/VBUS (input)
PTM4 (input)/NF (input)
PTM3 (input/output)
PTM2 (input/output)
PTM1 (input/output)
PTM0 (input/output)
Figure 20.12 Port M
Rev. 2.00, 09/03, page 521 of 690