HD6417705F133V Datasheet, PDF (197/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Bus State Controller (BSC)
7.1 Overview
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. BSC functions enable this LSI to
connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
7.1.1 Features
The BSC has the following features:
• Physical address space is divided into eight areas
 A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
CS6A and CS6B, totally 384 Mbytes.
 Can specify the normal space interface, byte-selection SRAM interface, burst ROM,
address/data multiplex I/O (MPX), or SDRAM for each address space.
 Can select the data bus width (8, 16, or 32 bits) for each address space.
 Controls the insertion of the wait state for each address space.
 Controls the insertion of the wait state for each read access and write access.
 Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), the first cycle is a
write access.
• Normal space interface
 Supports the interface that can directly connect to the SRAM.
• Burst ROM interface
 High-speed access to the ROM, such as flash memory, that has the page mode function.
• Address/data multiplex I/O (MPX) interface
 Can directly connect to a peripheral LSI that needs an address/data multiplexing.
• SDRAM interface
 Can set the SDRAM up to 2 areas.
 Multiplex output for row address/column address.
 Efficient access by single read/single write.
 High-speed access by the bank-active mode.
 Supports an auto-refresh and self-refresh.
BSCS311A_000020020100
Rev. 2.00, 09/03, page 149 of 690