HD6417705F133V Datasheet, PDF (389/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Initial
Bit
Bit Name Value R/W Description
0
TGFA
0
R/(W)^* Output Compare Flag A
Status flag that indicates the occurrence of TGRA compare
match.
[Clearing condition]
When 0 is written to TGFA after reading TGFA = 1
[Setting condition]
When TCNT = TGRA
Note: * Only 0 can be written for clearing the flags.
14.3.6 Timer Counters (TCNT)
TCNT are 16-bit counters.
The initial value of TCNT is H'0000.
14.3.7 Timer General Registers (TGR)
TGR are 16-bit registers.
TGRC and TGRD can also be designated for operation as buffer registers*. The initial value of
TGR is H'FFFF.
Note: *TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
14.3.8 Timer Start Register (TSTR)
TSTR is a 16-bit readable/writable register that selects TCNT operation/stoppage for channels 0 to
3.
Initial
Bit
Bit Name Value
15 to 4 
0
3
CST3
0
2
CST2
0
1
CST1
0
0
CST0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Counter Start
Select operation or stoppage for TCNT.
0: TCNTn count operation is stopped
1: TCNTn performs count operation
[Legend] n = 3 to 0
Rev. 2.00, 09/03, page 341 of 690