HD6417705F133V Datasheet, PDF (44/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Tables
Section 1 Overview
Table 1.1 SH7705 Features...................................................................................................... 2
Table 1.2 Pin Functions ........................................................................................................... 9
Table 1.3 Pin Functions ......................................................................................................... 17
Section 2 CPU
Table 2.1 Logical Address Space ........................................................................................... 28
Table 2.2 Register Initial Values ............................................................................................ 30
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions ........................... 42
Table 2.4 CPU Instruction Formats........................................................................................ 45
Table 2.5 CPU Instruction Types ........................................................................................... 48
Table 2.6 Data Transfer Instructions ...................................................................................... 52
Table 2.7 Arithmetic Operation Instructions........................................................................... 54
Table 2.8 Logic Operation Instructions .................................................................................. 56
Table 2.9 Shift Instructions.................................................................................................... 57
Table 2.10 Branch Instructions ............................................................................................ 58
Table 2.11 System Control Instructions................................................................................ 59
Table 2.12 Operation Code Map .......................................................................................... 62
Section 3 Memory Management Unit (MMU)
Table 3.1 Access States Designated by D, C, and PR Bits....................................................... 80
Section 4 Cache
Table 4.1 Number of Entries and Size/Way in Each Cache Size ............................................. 93
Table 4.2 LRU and Way Replacement (when Cache Locking Mechanism Is Disabled)........... 95
Table 4.3 Way Replacement when a PREF Instruction Misses the Cache................................ 99
Table 4.4 Way Replacement when Instructions other than
the PREF Instruction Miss the Cache...................................................................... 99
Table 4.5 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0).................... 99
Table 4.6 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1).................... 99
Table 4.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1).................. 100
Table 4.8 Address Format Based on Size of Cache to be Assigned to Memory...................... 106
Section 5 Exception Handling
Table 5.1 Exception Event Vectors ...................................................................................... 116
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration................................................................................................. 127
Table 6.2 Interrupt Sources and IPRA to IPRH..................................................................... 128
Table 6.3 IRL3 to IRL0 Pins and Interrupt Levels ................................................................ 138
Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)............................ 140
Rev. 2.00, 09/03, page xlii of xlvi