HD6417705F133V Datasheet, PDF (387/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.3.4 Timer Interrupt Enable Registers (TIER)
TIER are 16-bit registers that control enabling or disabling of interrupt requests for each channel.
Initial
Bit
Bit Name Value
15 to 5 
0
4
TCIEV 0
3
TGIED 0
2
TGIEC 0
1
TGIEB 0
0
TGIEA 0
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Overflow Interrupt Enable
Enables or disables interrupt requests by the TCFV bit when
the TCFV bit in TSR is set to 1 (TCNT overflow).
0: Interrupt requests by TCFV disabled
1: Interrupt requests by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests by the TGFD bit when
the TGFD bit in TSR is set to 1 (TCNT and TGRD compare
match).
0: Interrupt requests by TGFD disabled
1: Interrupt requests by TGFD enabled
TGR Interrupt Enable C
Enables or disables interrupt requests by the TGFC bit when
the TGFC bit in TSR is set to 1 (TCNT and TGRC compare
match).
0: Interrupt requests by TGFC disabled
1: Interrupt requests by TGFC enabled
TGR Interrupt Enable B
Enables or disables interrupt requests by the TGFB bit when
the TGFB bit in TSR is set to 1 (TCNT and TGRB compare
match).
0: Interrupt requests by TGFB disabled
1: Interrupt requests by TGFB enabled
TGR Interrupt Enable A
Enables or disables interrupt requests by the TGFA bit when
the TGFA bit in TSR is set to 1 (TCNT and TGRA compare
match).
0: Interrupt requests by TGFA disabled
1: Interrupt requests by TGFA enabled
Rev. 2.00, 09/03, page 339 of 690