HD6417705F133V Datasheet, PDF (298/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

8.3.6 DMA Extended Resource Selectors 0, 1 (DMARS0, DMARS1)
DMARS is a 16-bit readable/writable register that specifies the DMA transfer request sources
from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 for
channels 2 and 3. This register can set the transfer request of SCIF0, SCIF2, and USB.
When MID/RID other than the values listed in table 8.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) has been set to B'1000 for CHCR_0 to CHCR_3. Otherwise, even if DMARS has been set,
transfer request source is not accepted.
• DMARS0
Bit
Bit
Name
15
C1MID5
14
C1MID4
13
C1MID3
12
C1MID2
11
C1MID1
10
C1MID0
9
C1RID1
8
C1RID0
Initial
Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
7
C0MID5 0
R/W
6
C0MID4 0
R/W
5
C0MID3 0
R/W
4
C0MID2 0
R/W
3
C0MID1 0
R/W
2
C0MID0 0
R/W
1
C0RID1 0
R/W
0
C0RID0 0
R/W
Description
Transfer request source module ID5 to ID0 for DMA channel
1 (MID)
See table 8.2.
Transfer request resource register ID1 to ID0 for DMA
channel 1 (RID)
See table 8.2.
Transfer request source module ID5 to ID0 for DMA channel
0 (MID)
See table 8.2
Transfer request resource register ID1 to ID0 for DMA
channel 0 (RID)
See table 8.2.
Rev. 2.00, 09/03, page 250 of 690