HD6417705F133V Datasheet, PDF (566/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

20.9 Port J
Port J is an 8-bit output port with the pin configuration shown in figure 20.9.
Port J
PTJ7 (output)/NF (output)
PTJ6 (output)/NF (output)
PTJ5 (output)/NF (output)
PTJ4 (output)/NF (output)
PTJ3 (output)/NF (output)
PTJ2 (output)/NF (output)
PTJ1 (output)/NF (output)
PTJ0 (output)/NF (output)
Figure 20.9 Port J
20.9.1 Register Description
Port J has the following register. For details on the register address and access size, see section 24,
List of Registers.
• Port J data register (PJDR)
20.9.2 Port J Data Register (PJDR)
PJDR is an 8-bit readable/writable register that stores data for pins PTJ7 to PTJ0. Bits PJ7DT to
PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general output port, if the port
is read, the value of the corresponding PJDR bit is returned directly.
Bit
Initial
Bit Name Value R/W
7 to 0 PJ7DT 0
R/W
to
PJ0DT
Description
Table 20.9 shows the function of PJDR.
Rev. 2.00, 09/03, page 518 of 690