HD6417705F133V Datasheet, PDF (628/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

TCK
TDO
(when the UDI
command is set)
TDO
(when the boundary scan
command is set)
t_TDO
t_TDO
Figure 23.3 UDI Data Transfer Timing
23.4.4 UDI Reset
An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the
same kind as a power-on reset. An UDI reset is released by inputting an UDI reset negate
command. The required time between the UDI reset assert command and UDI reset negate
command is the same as time for keeping the RESETP pin low to apply a power-on reset.
SDIR
UDI reset assert
UDI reset negate
Chip internal reset
CPU state
Branch to H'A0000000
Figure 23.4 UDI Reset
23.4.5 UDI Interrupt
The UDI interrupt function generates an interrupt by setting a command from the UDI in the
SDIR. An UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
UDI interrupts are accepted in sleep mode, but not in standby mode.
Rev. 2.00, 09/03, page 580 of 690