HD6417705F133V Datasheet, PDF (459/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

c. Serial Data Reception
Figures 16.7 and 16.8 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read DR, ER, and BRK flags in SCSSR [1]
Yes
DR V ER V BRK = 1?
No
Error handling
Read RDF flag in SCSSR
[2]
No
RDF = 1?
Yes
Read receive data from SCFRDR,
and clear RDF flag in SCSSR to 0
[3]
No
All data received?
Yes
Clear RE bit in SCSCR to 0
[1] Receive error handling and break detection:
Read the DR, ER, and BRK flags in SCSSR to
identify any error, perform the appropriate error
handling, then clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break can also be
detected by reading the value of the RxD pin.
[2] SCIF status check and receive data read:
Read SCSSR and check that RDF = 1, then read the
receive data in SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The transition of the
RDF flag from 0 to 1 can also be identified by an RXI
interrupt.
[3] Serial reception continuation procedure:
To continue serial reception, read at least the receive
trigger set number of data bytes from SCFRDR, read
1 from the RDF flag, and then clear the RDF flag to
0. The number of receive data bytes in SCFRDR can
be ascertained by reading the lower bits of SCFDR.
End of reception
Figure 16.7 Sample Serial Reception Flowchart (1)
Rev. 2.00, 09/03, page 411 of 690