HD6417705F133V Datasheet, PDF (177/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.3.2 Interrupt Control Register 0 (ICR0)
ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and
indicates the input signal level at the NMI pin.
Bit
Bit Name Initial Value R/W Description
15
NMIL
0/1^*
R
NMI Input Level
Sets the level of the signal input at the NMI pin.
This bit can be read from to determine the NMI
pin level. This bit cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
8
NMIE
0
R/W NMI Edge Select
Selects whether the falling or rising edge of the
interrupt request signal at the NMI pin is
detected.
0: Interrupt request is detected on falling edge of
NMI input
1: Interrupt request is detected on rising edge of
NMI input
7 to 0 
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * When NMI input is high, 0 when NMI input is low.
Rev. 2.00, 09/03, page 129 of 690