HD6417705F133V Datasheet, PDF (167/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• Exception code
An exception occurred during read: H'0E0
An exception occurred during write: H'1E0
• Remarks
The logical address (32 bits) that caused the exception is set in TEA.
Illegal General Instruction Exception:
• Conditions
 When undefined code not in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Note: For details on undefined code, refer to section 2.6.2, Operation Code Map. When an
undefined code other than H'F000 to H'FFFF is decoded, operation cannot be guaranteed.
 When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
• Types
Instruction synchronous, re-execution type
• Save address
An instruction address where an exception occurs
• Exception code
H'180
• Remarks
None
Illegal Slot Instruction:
• Conditions
 When undefined code in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
 When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
 When an instruction that rewrites PC in a delay slot is decoded
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
• Types
Instruction synchronous, re-execution type
Rev. 2.00, 09/03, page 119 of 690