HD6417705F133V Datasheet, PDF (193/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with INTEVT or INTEVT2 value as its offset in order to identify the
interrupt source. This enables it to branch to the handling routine for the individual interrupt
source.
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
acceptance of an interrupt in this LSI.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, and then execute an RTE instruction.
Rev. 2.00, 09/03, page 145 of 690