HD6417705F133V Datasheet, PDF (300/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

8.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.
8.4.1 Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extended resource selector (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request is generated and transfer is enabled, the DMAC transfers 1 transfer
unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are
also aborted when the DE bit in CHCR or the DME bit in DMAOR are cleared to 0.
Rev. 2.00, 09/03, page 252 of 690