HD6417705F133V Datasheet, PDF (396/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

TCNT value
TGRB
TGRA
H'0000
N (A)
TGRC N (A)
N (B)
TGRA
N (A)
N (B)
N (TGRB+1)
N (B)
N (TGRB+1)
Time
N (TGRB+1)
TO pin
Figure 14.10 Example of Buffer Operation
14.4.4 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0 or 1 output can be selected as
the output level in response to compare match of each TGRA.
Designating TGRB compare match as the counter-clearing source enables the period to be set in
that register. All channels can be designated for PWM mode independently.
PWM output is generated from the TO pin using TGRB as the period register and TGRA as duty
cycle registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a period register compare match, the output value of each pin is the initial
value set in TIOR. Set TIOR so that the initial output and an output value by compare match are
different. If the same levels or toggle outputs are selected, operation is disabled.
Conditions of duty cycle 0% and 100% are shown below.
• Duty cycle 0%: The set value of the period register (TGRB) is TGRA + 1 for the duty
register (TGRA).
• Duty cycle 100%: The set value of the duty register (TGRA) is 0.
In PWM mode, a maximum 4-phase PWM output is possible.
Rev. 2.00, 09/03, page 348 of 690